
39
AT/TSC8x251G2D
4135F–8051–11/06
Table 32.
Summary of Call and Return Instructions
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.
2. In internal execution only, add 1 to the number of states if the destination/return
address is internal and odd.
3. Add 2 to the number of states if the destination address is external.
4. Add 5 to the number of states if INTR = 1.
Absolute callACALL <src>(PC)
← (PC) +2; push (PC)15:0;
(PC)10:0 ← src opnd
Extended callECALL <src>(PC)
← (PC) + size (instr); push (PC)23:0;
(PC)23:0 ← src opnd
Long callLCALL <src>(PC)
← (PC) + size (instr); push (PC)15:0;
(PC)15:0 ← src opnd
Return from subroutineRETpop (PC)15:0
Extended return from subroutineERETpop (PC)23:0
Return from interruptRETIIF [INTR = 0] THEN pop (PC)15:0
IF [INTR = 1] THEN pop (PC)23:0; pop (PSW1)
Trap interruptTRAP(PC)
← (PC) + size (instr);
IF [INTR = 0] THEN push (PC)15:0
IF [INTR = 1] THEN push (PSW1); push (PC)23:0
Mnemonic
<dest>,
<src>
(1)
Comments
Binary Mode
Source Mode
Bytes
States
Bytes
States
ACALL
addr11
Absolute subroutine call
2
9(2)(3)
29(2)(3)
ECALL
at DRk
Extended subroutine call (indirect)
3
14(2)(3)
213(2)(3)
addr24
Extended subroutine call
5
14(2)(3)
413(2)(3)
LCALL
at WRj
Long subroutine call (indirect)
3
10(2)(3)
29(2)(3)
addr16
Long subroutine call
3
9(2)(3)
39(2)(3)
RET
Return from subroutine
1
7(2)
17(2)
ERET
Extended subroutine return
3
9(2)
28(2)
RETI
Return from interrupt
1
7(2)(4)
17(2)(4)
TRAP
Jump to the trap interrupt vector
2
12(4)
111(4)